1. Field of the Invention
The present invention relates to a data recovery circuit that executes sampling of data with a clock superimposed in the communication data being separated so as to eliminate the influence of frequency deviations of a control clock of each unit in a case where communication is executed among units such as a servo unit.
2. Description of the Related Art
In a case where communication between units is executed, there are cases where a clock data recovery circuit is used which is a data recovery circuit executing sampling of data with a clock superimposed in communication data being separated so as to eliminate the influence of frequency deviations of a control clock of each unit. In a case where the clock data recovery circuit is included in an application specific integrated circuit (ASIC), the clock data recovery circuit is designed dedicatedly for an ASIC vendor. For this reason, in a case where another ASIC having a different communication frequency is generated, it is necessary to newly design a clock data recovery circuit, and accordingly, the development period is long. Here, the ASIC is a customized integrated circuit and is an integrated circuit (IC) designed to have a function specialized for a specific use.
As a means for solving such a problem, for example, a data recovery circuit of an oversampling type disclosed in JP 2006-262165 A may be considered to be used. In such a data recovery circuit, a plurality of clocks having a frequency lower than the transmission rate of serial data are prepared by shifting the phase, and the serial data is sampled to be parallel data by using each clock, and accordingly, the frequency of the used clocks can be lowered, whereby a data recovery circuit can be easily designed.
In such a data recovery circuit of the oversampling type, as the number of times of oversampling for one bit of the serial data for serial communication increases, the sampling position for recovering the serial data can be finely adjusted, whereby the accuracy of recovery can be improved.
However, in the data recovery circuit of the oversampling type disclosed in JP 2006-262165 A, the data rate of the serial communication needs to be an integer multiple of the frequency of the parallel data output by the oversampling circuit such that the edge position of the parallel data acquired by oversampling the serial data is not changed much from the edge position of the previous time (for example, two bits of the serial communication is oversampled to be output as parallel data of one time). For this reason, in a case where the number of bits of the parallel data is determined, the oversampling frequency can be limited to a usable oversampling frequency, and there is a problem in that the number of times of oversampling cannot be set to a maximum value.
FIG. 9 is a diagram that illustrates a conventional data recovery circuit. The data recovery circuit 30 includes an oversampling unit 31, an edge detection unit 32, a sampling clock selection unit 33, a phase comparison unit 34, and a data sampling unit 35.
The oversampling unit 31 samples data received through serial communication by using a clock having a frequency higher than the communication rate of serial data and outputs parallel data (pdata) of n bits and a clock (rclk) having a frequency that is 1/n of the frequency of the clock described above.
In an example illustrated in FIG. 10, the oversampling unit 31 executes oversampling with a frequency that is six times the data rate of the serial communication and outputs two bits of serial communication data as parallel data (pdata) of 12 bits.
The edge detection unit 32 detects an edge position of parallel data (pdata) that is output by the oversampling unit 31. The sampling clock selection unit 33 selects a sampling clock among sampling clocks smpl_clk1 to smpl_clk6 prepared in advance in accordance with a phase control signal (cntdn, cntup) that is output by the phase comparison unit 34. In a case where there is no input of a phase control signal (a signal cntdn representing a change (increase) in the phase or a signal cntup representing a change (decrease) in the phase), the same sampling clock as that of the previous time is output. On the other hand, in a case where a phase control signal (cntdn, cntup) is input, a sampling clock that is increased by one or is decreased by one is output in accordance with the input signal.
The phase comparison unit 34 compares a position edgdata of an edge that is actually detected by the edge detection unit 32 with the edge position of the current sampling clock (smple_clk) and outputs a phase control signal (cntdn, cntup).
The data sampling unit 35 extracts recovery data by using the parallel data (pdata) output by the oversampling unit 31 and the sampling clock (smple_clk) output by the sampling clock selection unit 33 and outputs the extracted recovery data.
In the data recovery circuit 30, in order for the sampling clock selection unit 33 to select a sampling clock, it is necessary that the edge position of the parallel data (pdata) output by the oversampling unit 31 is not changed much from the edge position of the previous time. For this reason, the data rate of the serial communication needs to be an integer multiple of the frequency of the parallel data output by the oversampling unit 31. In a case where the parallel data (pdata) is configured by 12 bits, a maximum frequency that is 12 times the data rate of the serial communication can be used for the oversampling clock. However, in a case where the circuit of the oversampling unit 31 cannot be configured by using this frequency due to a problem of a setup hold time or the like, the oversampling clock (clk) has a frequency that is six times the data rate of the serial communication, and, in a case where the circuit cannot be configured even in such a case, the oversampling clock has a frequency that is four times the data rate, and there is a problem in that the frequency of the oversampling clock (clk) cannot be freely selected.
In addition, in an ASIC or an FPGA (the FPGA is an integrated circuit of which the configuration can be set by a purchaser or a designer after the manufacturing thereof), an IP core of high speed communication such as Gigabit Ethernet (registered trademark) that is generally used widely is prepared, and a means for increasing the number of times of oversampling in a simple manner, in other words, in an easy manner is included therein.